verilog - Code for non-resetable flop -

is acceptable way code non-resetable flop ?

input clk; input b;  output a; reg a= 1'b0;  always_ff @ (posedge clk)   if(b>a)     a<=b; 

non-resettable flops used everywhere.....!

the technical advantage of resettable flop can reach "known" state in finite machine using single transition on reset pin else might have go through multiple cycles on clock reach known state.

this needed when power on chip. there trade off between "no of cycles needed" area 1 has pay resettable flops.

moreover, mentioned at page.

in case of flops without set/reset pin, output deterministic if input d in known stable state @ arrival of clock , satisfies setup , hold requirement. during initial power up, output of such flops not initialized , in unknown state, treated x in digital simulation. remains x till first clock edge comes , along comes functional stable value @ input.

following implementation in verilog , yours in sv acceptable,

  @ (posedge sclk)      din_o <= din_i; 

keep in mind that, @ declaration, don't assign 0, works, see x if don't do. according me bad habit assign variable @ time of declaration.

you have comparator, until , unless condition true, a remain x, if try per above implementation(yours one) then, settled down 0 @ power-on.

silicon doesn't have x has 1, 0 , z only.